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DATA SHEET MOS INTEGRATED CIRCUIT
PD72852A
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
The PD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
FEATURES
* The two-port physical layer LSI complies with IEEE1394a-2000 * Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM) * Meets IntelTM Mobile Power Guideline 2000 * Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed concatenation, arbitration acceleration, fly-by concatenation * Suspend Debounce timer for ESD * "BIAS Detected" signal output * Double speed signal filter for BIAS Ringing * Small package: 64-pin plastic LQFP * Super low power : 68 mA (Operating mode) : 115 A (Suspend mode) * Data rate: 400/200/100 Mbps * Supports PHY pinging and remote PHY access packets * 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply) * 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency * 64-bit flexible register incorporated in PHY register * Electrically isolated Link interface * Supports LPS/Link-on as part of PHY/Link interface * External filter capacitors for PLL not required * Extended Resume signaling for compatibility with legacy DV devices * System power management by signaling of node power class information * Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number Package 64-pin plastic LQFP (10 x 10)
PD72852AGB-8EU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. Date Published Printed in Japan S16725EJ2V0DS00 (2nd edition) March 2004 NS CP (K)
The mark
shows major revised points.
2003
PD72852A
BLOCK DIAGRAM
CMC PC0 PC1 PC2 SUS/RES
TpA0p TpA0n
Cable Port0
LREQ LPS DIRECT SCLK LKON CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7
TpB0p TpB0n
Arbitration and Control State Machine Logic Link Interface I/O
TpA1p TpA1n
Cable Port1 TpB1p TpB1n
BDB
Receive Data Decoder and Retimer
Voltage and Current Generator Crystal Oscillator PLL System and Transmit Clock Generator
TpBias0 TpBias1 RI1
RESETB CPS Cable Power Status
Transmit Data Encoder
XI XO
2
Data Sheet S16725EJ2V0DS
PD72852A
PIN CONFIGURATION (Top View)
* PD72852AGB-8EU 64-pin plastic LQFP (10 x 10)
SPD/BDB
RESETB
DGND
DGND
DIRECT 50
AGND
AGND
FNSel
LREQ
DVDD
LKON
DVDD
64
63
62
61
60
59
58
57
56
55
54
AVDD
LPS
53
52
51
DGND SCLK IC(DL) DVDD CTL0 CTL1 DGND D0 D1 DVDD D2 D3 DGND D4 D5 DGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
AGND
IC(AL)
TpBias1 AVDD TpA1p TpA1n TpB1p TpB1n AGND TpBias0 AVDD TpA0p TpA0n TpB0p TpB0n AGND RI1 AGND
SUS/RES
AGND
DGND
DVDD
CMC
XO
AVDD
IC(AL)
AVDD
PC0
PC1
PC2
D6
D7
CPS
XI
Data Sheet S16725EJ2V0DS
3
PD72852A
PIN NAME
AGND AVDD CMC CPS CTL0 CTL1 D0-D7 DGND DIRECT DVDD FNSel IC(AL) IC(DL) LKON LPS LREQ PC0-PC2 RESETB RI1 SCLK SPD/BDB SUS/RES TpA0n TpA0p TpA1n TpA1p TpB0n TpB0p TpB1n TpB1p TpBias0 TpBias1 XI XO : Analog GND : Analog Power : Configuration Manager Capable : Cable Power Status : Link Interface Control (bit 0) : Link Interface Control (bit 1) : Data Input/Output : Digital GND : PHY/Link Isolation Barrier Control Input : Digital VDD : Function Select : Internally Connected (Low Clamped) : Internally Connected (Low Clamped) : Link-on Signal Output : Link Power Status Input : Link Request Input : Power Class Set Input : Power-on Reset Input : Reference Power Set, Connect Resistor 1 : Link Control Output Clock : Speed Select input / BIAS Detected output : Suspend/Resume Function Select : Port 0 Twisted Pair Cable A Negative Phase I/O : Port 0 Twisted Pair Cable A Positive Phase I/O : Port 1 Twisted Pair Cable A Negative Phase I/O : Port 1 Twisted Pair Cable A Positive Phase I/O : Port 0 Twisted Pair Cable B Negative Phase I/O : Port 0 Twisted Pair Cable B Positive Phase I/O : Port 1 Twisted Pair Cable B Negative Phase I/O : Port 1 Twisted Pair Cable B Positive Phase I/O : Port 0 Twisted Pair Output : Port 1 Twisted Pair Output : Crystal Oscillator Connection XI : Crystal Oscillator Connection XO
4
Data Sheet S16725EJ2V0DS
PD72852A
CONTENTS 1. PIN 1.1 1.2 1.3 1.4 1.5 1.6 FUNCTIONS..................................................................................................................................... 7 Cable Interface Pins ........................................................................................................................ 7 Link Interface Pins .......................................................................................................................... 7 Control Pins ..................................................................................................................................... 8 IC ....................................................................................................................................................... 8 Power Supply Pins .......................................................................................................................... 8 Other Pins ........................................................................................................................................ 9
2. PHY REGISTERS .................................................................................................................................. 10 2.1 Complete Structure for PHY Registers ....................................................................................... 10 2.2 Port Status Page (Page 000) ........................................................................................................ 13 2.3 Vendor ID Page (Page 001)........................................................................................................... 14 2.4 Vendor Dependent Page (Page 111 : Port_select 0000)............................................................ 14 2.5 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................ 15 3. INTERNAL FUNCTION.......................................................................................................................... 16 3.1 Link Interface ................................................................................................................................. 16
3.1.1 Connection Method ............................................................................................................................... 16 3.1.2 LPS (Link Power Status) ....................................................................................................................... 16 3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins..................................................................................................... 16 3.1.4 SCLK..................................................................................................................................................... 16 3.1.5 LKON .................................................................................................................................................... 17 3.1.6 DIRECT................................................................................................................................................. 17 3.1.7 Isolation Barrier ..................................................................................................................................... 17
3.2 Cable Interface............................................................................................................................... 19
3.2.1 Connections .......................................................................................................................................... 19 3.2.2 Cable Interface Circuit........................................................................................................................... 20 3.2.3 Unused Ports ........................................................................................................................................ 20 3.2.4 CPS....................................................................................................................................................... 20
3.3 Suspend/Resume .......................................................................................................................... 20
3.3.1 Suspend/Resume On Mode (SUS/RES = "H")...................................................................................... 20 3.3.2 Suspend/Resume Off Mode (SUS/RES = "L") ...................................................................................... 20
3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 21
3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 21 3.4.2 PLL........................................................................................................................................................ 21
3.5 3.6 3.7 3.8
CMC ................................................................................................................................................ 21 PC0-PC2 ......................................................................................................................................... 21 RESETB .......................................................................................................................................... 21 RI1 ................................................................................................................................................... 21
4. PHY/LINK INTERFACE ......................................................................................................................... 22 4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................ 22 4.2 Link-on Indication ......................................................................................................................... 23 4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ...................................................... 24
4.3.1 CTL0, CTL1 .......................................................................................................................................... 24 4.3.2 LREQ .................................................................................................................................................... 24
Data Sheet S16725EJ2V0DS
5
PD72852A
4.3.3 SCLK Timing ......................................................................................................................................... 28
4.4 4.5 4.6 4.7 4.8
Acceleration Control ..................................................................................................................... 29 Transmit Status ............................................................................................................................. 30 Transmit ......................................................................................................................................... 31 Cancel............................................................................................................................................. 32 Receive ........................................................................................................................................... 33
5. CABLE PHY PACKET ........................................................................................................................... 34 5.1 Self_ID Packet................................................................................................................................ 34 5.2 Link-on Packet............................................................................................................................... 35 5.3 PHY Configuration Packet............................................................................................................ 35 5.4 Extended PHY Packet ................................................................................................................... 35
5.4.1 Ping Packet ........................................................................................................................................... 36 5.4.2 Remote Access Packet ......................................................................................................................... 36 5.4.3 Remote Reply Packet............................................................................................................................ 37 5.4.4 Remote Command Packet .................................................................................................................... 37 5.4.5 Remote Confirmation Packet ................................................................................................................ 38 5.4.6 Resume Packet..................................................................................................................................... 38
6. ELECTRICAL SPECIFICATIONS ......................................................................................................... 39 7. APPLICATION CIRCUIT EXAMPLE ..................................................................................................... 44 8. PACKAGE DRAWING........................................................................................................................... 45 9. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 46
6
Data Sheet S16725EJ2V0DS
PD72852A
1. PIN FUNCTIONS 1.1 Cable Interface Pins
Name TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n SUS/RES Pin No. 39 38 37 36 46 45 44 43 19 I/O I/O I/O I/O I/O I/O I/O I/O I/O I Function Port 0 twisted pair cable A positive phase I/O Port 0 twisted pair cable A negative phase I/O Port 0 twisted pair cable B positive phase I/O Port 0 twisted pair cable B negative phase I/O Port 1 twisted pair cable A positive phase I/O Port 1 twisted pair cable A negative phase I/O Port 1 twisted pair cable B positive phase I/O Port 1 twisted pair cable B negative phase I/O Suspend/Resume function select 1: Suspend/Resume on (IEEE1394a-2000 compliant) 0: Suspend/Resume off (P1394a draft 1.3 compliant) CPS 32 I Cable power status Connect to the cable through a 390 k resistor and to GND through a 100 k resistor. 0: Cable power fail 1: Cable power on
1.2 Link Interface Pins
Name D0 D1 D2 D3 D4 D5 D6 D7 CTL0 CTL1 LREQ SCLK 8 9 11 12 14 15 17 18 5 6 63 2 Pin No. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O Data input/output (bit 0) Data input/output (bit 1) Data input/output (bit 2) Data input/output (bit 3) Data input/output (bit 4) Data input/output (bit 5) Data input/output (bit 6) Data input/output (bit 7) Link interface control (bit 0) Link interface control (bit 1) Link request input Link control output clock LPS 1: 49.152 MHz output LPS 0: Clamp to 0 (The clock signal will be output within 25 sec after change to "0") LPS 59 I Link power status input 0: Link power off 1: Link power on (PHY/Link direct connection) LKON 58 O Link-on signal output Link-on signal is 6.144 MHz clock output. Please refer to 4.2 Link-on Indication. DIRECT 50 I PHY/Link isolation barrier control input 0: Isolation barrier 1: PHY/Link direct connection Function
Data Sheet S16725EJ2V0DS
7
PD72852A
1.3 Control Pins
Name PC0 PC1 PC2 CMC Pin No. 26 27 28 30 I/O I I I I Power class set input This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H. IEEE1394a-2000 chapter [4.3.4.1] Configuration manager capable setting This pin status will be loaded to Contender bit which allocated to PHY register 4H. 0: Non contender 1: Contender RESETB 55 I Power-on reset input Connect to GND through a 0.1 F capacitor. 0: Reset 1: Normal FNSel 62 I Function Select 0: #61 acts as SPD 1: #61 acts as BDB SPD 61 I Speed select ( When FNSel set to 0 ; PD72852A compliant) 0: MAX. S200 1: MAX. S400 BDB 61 O BIAS Detected (Logical Inverse) 0: BIAS is detected after suspend debounce timer. 1: BIAS is not detected. Function
1.4 IC
Name IC(AL) IC(DL) Pin No. 29, 51 3 I/O Internally Connected (Low Clamped) Connect to GND. Internally Connected (Low Clamped) Connect to GND. Function
1.5 Power Supply Pins
Name AVDD AGND DVDD DGND Pin No. 25, 31, 40, 47, 54 24, 33, 35, 42, 49, 52, 53 4, 10, 20, 56, 60 1, 7, 13, 16, 21, 57, 64 I/O Analog power Analog GND Digital VDD Digital GND Function
8
Data Sheet S16725EJ2V0DS
PD72852A
1.6 Other Pins
Name TpBias0 TpBias1 RI1 XI XO Pin No. 41 48 34 23 22 I/O O O Port 0 twisted pair output Port 1 twisted pair output Resistor connection pin1 for reference current generator Connect to GND through a 9.1 k resistor. Crystal oscillator connection XI Crystal oscillator connection XO Function
Data Sheet S16725EJ2V0DS
9
PD72852A
2. PHY REGISTERS 2.1 Complete Structure for PHY Registers
Figure 2-1. Complete Structure of PHY Registers
0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Page_select Link_active Watchdog RHB IBR Extended (7) Max_speed Contender ISBR Loop Reserved Reserved Jitter Pwr_fail Timeout Port_event 1 2 Physical_ID Gap_count Total_ports Delay Pwr_class Enab_accel Enab_multi 3 4 5 6 R 7 PS
Reserved Reserved Register0 (page_select) Register1 (page_select) Register2 (page_select) Register3 (page_select) Register4 (page_select) Register5 (page_select) Register6 (page_select) Register7 (page_select) Port_select
Table 2-1. Bit Field Description (1/3)
Field Physical_ID R Size 6 1 R/W R R Reset value 000000 0 Description Physical_ID value selected from Self_ID period. If this bit is 1, the node is root. 1: Root 0: Not root PS 1 R Cable power status. 1: Cable power on 0: Cable power off RHB IBR 1 1 R/W R/W 0 0 Root Hold -off bit. If 1, becomes root at the bus reset. Initiate bus reset. Setting to 1 begins a long bus reset. Long bus reset signal duration: 166 sec. Returns to 0 at the beginning of bus reset. Gap_count 6 R/W 111111 Gap count value. It is updated by the changes of transmitting and receiving the PHY configuration packet Tx/Rx. The value is maintained after first bus reset. After the second bus reset it returns to reset value. Extended 3 R 111 Shows the extended register map.
10
Data Sheet S16725EJ2V0DS
PD72852A
Table 2-1. Bit Field Description (2/3)
Field Total_ports Max_speed Size 4 3 R/W R R Reset value 0010 See Description Supported port number. 0010: 2 ports Indicate the maximum speed that this node supports. Set variable by SPD pin (61 pin). When SPD = "0" then 001: 98.304 and 196.608 Mbps. When SPD = "1" then 010: 98.304, 196.608 and 393.216 Mbps. Delay Link_active 4 1 R R/W 0000 1 Indicate worst case repeating delay time. 144 + (Delay x 20) = 144 nsec Link active. 1: Enable 0: Disable The logical AND status of this bit and LPS pin. State will be referred to "L bit" of Self-ID Packet#0. Contender 1 R/W See Description Contender. "1" indicate this node support bus manager function. This bit will be referred to "C bit" of Self-ID Packet#0. The reset data is depending on CMC pin setting. CMC pin condition 1: Pull up (Contender) 0: Pull down (Non Contender) Jitter Pwr_class 3 3 R R/W 010 See Description The difference of repeating time (Max.-Min.). (2+1) x 20 = 60 nsec Power class. Please refer to IEEE1394a-2000 [4.3.4.1]. This bit will be referred to Pwr field of Self-ID Packet#0. The reset data will be determined by PC0-PC2 Pin status. Watchdog 1 R/W 0 Watchdog Enable. This bit serves two purposes. When set to 1, if any one port does resume, the Port_event bit becomes 1. This function has no effect when SUS/RES (19 pin) = "0". To determine whether or not an interrupt condition shall be indicated to the Link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop, Pwr_fail, Timeout is not output. This function has effect both when SUS/RES (19 pin) = "1" or "0". ISBR 1 R/W 0 Initiate short (arbitrated) bus reset. Setting to 1 acquires the bus and begins short bus reset. Short bus reset signal output : 1.3 sec Returns to 0 at the beginning of the bus reset. Loop 1 R/W 0 Loop detection output. 1: Detection Writing 1 to this bit clears it to 0. Writing 0 has no effect. Pwr_fail 1 R/W 1 Power cable disconnect detect. It becomes 1 when there is a change from 1 to 0 in the CPS bit. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Description
Data Sheet S16725EJ2V0DS
11
PD72852A
Table 2-1. Bit Field Description (3/3)
Field Timeout Size 1 R/W R/W Reset value 0 Description Arbitration state machine time-out. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Port_event 1 R/W 0 Set to 1 when the Int_enable bit in the register map of each port is 1 and there is a change in the ports connected, Bias, Disabled and Fault bits. Set to 1 when the Watchdog bit is 1 and any one port does resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. This bit is not settable when SUS/RES (19 pin) = "0". Enab_accel 1 R/W 0 Enables arbitration acceleration. Ack-acceleration and Fly-by arbitration are enabled. 1: Enabled 0: Disabled If this bit changes while the bus request is pending, the operation is not guaranteed. Enab_multi 1 R/W 0 Enable multi-speed packet concatenation. Setting this bit to 1 follows multi-speed transmission. When this bit is set to 0,the packet will be transmitted with the same speed as the first packet. Page_select 3 R/W 000 Select page address between 1000 to 1111. 000: Port Status Page 001: Vendor ID Page 111: Vendor Dependent Page Others: Unused Port_select 4 R/W 0000 Port Selection. Selecting 000 (Port Status Page) with the Page_select selects the port. Selecting 111 (Vendor Dependent Page) with the Page_select have to select the Port 1. 0000: Port 0 0001: Port 1 Others: Unused Reserved R 000... Reserved. Read as 0.
12
Data Sheet S16725EJ2V0DS
PD72852A
2.2 Port Status Page (Page 000)
Figure 2-2. Port Status Page
0 1000 1001 1010 1011 1100 1101 1110 1111 AStat Negotiated_speed 1 2 BStat Int_enable 3 4 Child Fault 5 Connected 6 Bias Reserved 7 Disabled
Reserved Reserved Reserved Reserved Reserved Reserved
Table 2-2. Bit Field Description
Field AStat Size 2 R/W R Reset value XX A port status value. 00: invalid, 10: "0" 01: "1", 11: "Z" BStat 2 R XX B port status value. 00: invalid, 10: "0" 01: "1", 11: "Z" Child 1 R Child node status value. 1: Connected to child node 0: Connected to parent node Connected 1 R 0 Connection status value. 1: Connected 0: Disconnected Bias 1 R Bias voltage status value. 1: Bias voltage 0: No bias voltage Disabled Negotiated_ speed 1 3 R/W R See Description Shows the maximum data transfer rate of the node connected to this port. 000: 100 Mbps 001: 200 Mbps 010: 400 Mbps Int_enable 1 R/W 0 When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias, Disabled or Fault bits change state. This bit has no effect when SUS/RES (19 pin) = "0". Fault 1 R/W 0 Set to 1 if an error occurs during Suspend/Resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. This bit has no effect when SUS/RES (19 pin) = "0" Reserved R 000... Reserved. Read as 0. The reset value is set to 0: Enabled. Description
Data Sheet S16725EJ2V0DS
13
PD72852A
2.3 Vendor ID Page (Page 001)
Figure 2-3. Vendor ID Page
0 1000 1001 1010 1011 1100 1101 1110 1111 Product_ID Vendor_ID 1 2 3 4 5 6 7
Compliance_level Reserved
Table 2-3. Bit Field Description
Field Compliance_level Vendor_ID Product_ID Reserved Size 8 24 24 R/W R R R R 000... Reset value 00000001 00004CH According to IEEE1394a-2000. Company ID Code value, NEC IEEE OUI. Product code. Reserved. Read as 0. Description
2.4 Vendor Dependent Page (Page 111 : Port_select 0000)
Figure 2-4. Vendor Dependent Page
0 1000 1001 1010 1011 1100 1101 1110 1111 Rerserved Reserved 1 2 3 Reserved Long Debounce Reserved W_SPD_ DIS 4 5 6 7
Reserved
14
Data Sheet S16725EJ2V0DS
PD72852A
Table 2-4. Bit Field Description
Field Long Debounce W_SPD_DIS Size 2 1 R/W R/W R/W Reset value 00b 0 Description 00: suspend debounce timer sets to 420 ns 11: suspend debounce timer sets to 1000 ns. 0: NOT Receive Double speed signal Only First speed signal will be repeated for next port and packet will be decoded by highest speed within received. 1: Receive Double speed signal (IEEE1394a-2000 complient). Second speed signal will be applied for repeating /decoding.
2.5 Vendor Dependent Page (Page 111 : Port_select 0001)
Figure 2-5. Vendor Dependent Page contd.
0 1000 1001 1010 1011 1100 1101 1110 1111 Reg_array 1 2 3 4 5 6 7
Table 2-5. Bit Field Description
Field Reg_array Size 64 R/W R/W Reset value 0 Description This register array is possible R/W.
Data Sheet S16725EJ2V0DS
15
PD72852A
3. INTERNAL FUNCTION 3.1 Link Interface
3.1.1 Connection Method
Figure 3-1. PHY/Link Connection Method
D0-D7 CTL0,CTL1 LREQ SCLK LPS LKON PHY
Link
PD72852A
DIRECT
Note
Note Clamping to VDD provides direct connection to Link. Clamping to GND connects through isolation barrier to Link. The isolation barrier connection circuit is described in 3.1.7 Isolation Barrier. 3.1.2 LPS (Link Power Status) LPS is a function to monitor the On/Off status of the Link power supply. After 1.2 sec or more, LPS is Low, the PHY/Link is reset and D and CTL are output Low (when the isolation barrier is Hi-Z). After 2.5 sec or more, LPS is Low, moreover, the PHY stops the supply of SCLK and SCLK outputs Low (when the isolation barrier is Hi-Z). 3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins LREQ D0-D7 : Indicates that a request is received from Link. : Bi-directional pin which controls the data Transfer/Receive status signal, and the speed code Transfer/Receive status signal. 3.1.4 SCLK 49.152 MHz clock supplied by PHY for the PHY/Link interface synchronization. CTL0, CTL1 : Bi-directional pin which controls the functions between the PHY/Link interface.
16
Data Sheet S16725EJ2V0DS
PD72852A
3.1.5 LKON When the Link power is off, it outputs a clock of 6.144 MHz. LKON outputs under the following conditions: LPS is Low and the internal PHY register of the Link_active bit is 0. * Link-on packet is received. * Any bit of Loop, Pwr_fail, Timeout or Port_event is the PHY internal register becomes 1, and moreover either LPS or Link_active bit is 0. When LPS is asserted, LKON returns to Low. 3.1.6 DIRECT Set DIRECT to Low for using the isolation barrier. 3.1.7 Isolation Barrier The IEEE1394 cable holds signals for Data/Strobe in addition to power and ground. When the ground potential is different between connecting devices, the DC and AC current flows through the ground line in the cable and there is a possibility of malfunction due to ground difference between the two PHY. The PD72852A uses the isolation barrier to couple the AC between the PHY/Link interface to overcome the ground difference problem. Connecting the DIRECT pin to Low enables the digital differential circuit of the
PD72852A. The differential circuit propagates only the change in the signal; the interface will be driven only during
transitions High Low or Low High. The interface will assume the high impedance state when there is no signal change. The PD72852A uses Schmitt trigger input buffers for D, CTL, LREQ and LPS pins to prevent noise when the bus assumes a high impedance state. The digital differential circuit and the Schmitt trigger input buffers are needed on the Link layer controller LSI to implement the isolation barrier.
Figure 3-2. Waveforms of the Isolation Barrier
Isolation Barrier not used
0 1 1 0 0 0 1 0 0
Using Isolation Barrier (Digital differential circuit)
0 1 Z 0 Z Z 1 0 Z
Data Sheet S16725EJ2V0DS
17
PD72852A
Figure 3-3. Isolation Barrier Circuits
(a)
CTL0, CTL1, D0-Dn Isolation Barrier Circuit
LinkVDD 5 k 100 0.001 F 5 k LinkGND Required when LinkVDD is 5 V DVDD PD72852A 5.6 k 0.001 F 4.7 k 300 GND
Link
LinkGND
(b)
Link
Link-on Isolation Barrier Circuit
LinkVDD
PD72852A
100 5 k 0.01 F 1.6 k LinkGND
(c)
Link
LPS Isolation Barrier Circuit
DVDD 5 k 0.033 F 1.6 k GND 100
PD72852A
(d)
LREQ Isolation Barrier Circuit
Required when LinkVDD is 5 V
Link
LinkVDD 5 k 100 0.001 F 5 k LinkGND
DVDD 5.6 k 0.001 F 4.7 k 300 GND
PD72852A
LinkGND
(e)
Link
SCLK Isolation Barrier Circuit
DVDD 5 k
LinkVDD 5 k 0.001 F 5 k LinkGND
PD72852A
5 k GND
The Operating range of the power supply voltage is between 3.0 V and 3.45 V. Please refer to IEEE1394a-2000 [5A.8.4].
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Data Sheet S16725EJ2V0DS
PD72852A
3.2 Cable Interface
3.2.1 Connections
Figure 3-4. Cable Interface
Connection Detection Current Connection Detection Comparator Common Mode Speed Current Driver
+ - Driver
TpBias TpAp 7 k 7 k TpAn 56 56 56 56 TpBp 7 k 7 k TpBn 270 pF Receiver + - Arbitration Comparators + - + - TpBias Detection Comparator + - Connection Detection Current Connection Detection Comparator Driver
Receiver + - Arbitration Comparators + - + - Common Mode Comparators + - + -
1 F
5.1 k
Common Mode Speed Current Driver
TpBias TpBp Driver 7 k 7 k TpBn Receiver + - Arbitration Comparators + - + - TpBias Detection Comparator + - 270 pF 56 56 56 56 TpAp 7 k 7 k TpAn 1 F
+ - Driver
5.1 k
Receiver + - Arbitration Comparators + - + - + - + - Common Mode Comparators
Data Sheet S16725EJ2V0DS
19
PD72852A
3.2.2 Cable Interface Circuit
Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded, converted from parallel to serial and transmitted. While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel after synchronization by SCLK, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of 100/200/400 Mbps. The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of the IEEE1394 bus is transmitted to the state machine in the LSI.
3.2.3 Unused Ports
TpAp, TpAn : Not connected TpBp, TpBn : GND TpBias : Not connected
3.2.4 CPS
Connect an external resistor of 390 k between the CPS pin and the power cable, and an external resistor of 100 k between the CPS pin and GND to monitor the power of the power cable. If the cable power falls under 7.5 V there is an indication to the Link layer controller that the power has failed.
3.3 Suspend/Resume
3.3.1 Suspend/Resume On Mode (SUS/RES = "H")
There are two ways of transition from the active status to the suspended status. One is when the receipt of a remote command packet that sets the initiate suspend command. After that, the PHY transmits a remote confirmation packet with the ok bit set, subsequently signals TX_SUSPEND to the connected peer PHY with the port which specified by the port field in the remote command packet, and then the PHY port transitions to the suspended state. The other is when the receipt of a RX_SUSPEND or RX_DISABLE_NOTIFY signal. When the port observes RX_SUSPEND, it transmits TX_SUSPEND to the active ports. The TX_SUSPEND transmitted propagates until it reaches a leaf node. The PHY port transitions to the suspended state. The propagation of the suspended domain may be blocked by a PHY compliant with IEEE1394a-2000, a disabled or a suspended port. Any one of a number of reasons may cause a suspended port to attempt to resume normal operations: * Bias is detected and there is no fault condition; * A resume packet is received or transmitted by the PHY; * A remote command packet that sets the resume port command is received; or * Either port of a node without active ports detects bias.
3.3.2 Suspend/Resume Off Mode (SUS/RES = "L")
* Remote command packet is ignored. * Resume packet is ignored. * Disabled, Int_enable and resume_int bits in PHY register are ignored. * Responses to Remote access packet. * Detects the connection of the port in TpBias. * Output the 1.85 V voltage of the port in TpBias.
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Data Sheet S16725EJ2V0DS
PD72852A
3.4 PLL and Crystal Oscillation Circuit
3.4.1 Crystal Oscillation Circuit
To supply the clock of 24.576 MHz 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.
3.4.2 PLL
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
3.5 CMC
CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit in the PHY register when the input is High. The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Poweron Reset. Use a pull-up or pull-down resistor of 10 k, based on the device's specification.
3.6 PC0-PC2
The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to Section 4.3.4.1 of the IEEE1394a-2000 specification for information regarding the Pwr_class. The value of Pwr can be changed with software through the Link layer controller; this pin sets the initial value during Power-on Reset. Use a pull-up or pull-down resistor of 10 k based on the application.
3.7 RESETB
Connect an external capacitor of 0.1 F between the RESETB pin and GND. If the voltage drops below 0 V, a reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
3.8 RI1
Connect an external resistor of 9.1 k between the RI1 pin and GND to limit the LSI's current.
Data Sheet S16725EJ2V0DS
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PD72852A
4. PHY/LINK INTERFACE 4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface
The LPS pin monitors the On/Off status of the Link power state. This pin is used during the PHY/Link interface Enable/Disable (initialization).
Reset
When the LPS input pin is Low for TLPS_RESET: * CTL0, CTL1 and D0-D7 output Low (When the isolation barrier is Hi-Z). * SCLK continuously supplies the clock signal to the Link.
Disable
When the LPS input pin is Low for TLPS_DISABLE: * CTL0, CTL1, D0-D7 continue to output Low as TLPS_RESET has already occurred (When the isolation barrier is Hi-Z). * SCLK to Link stops and it outputs Low (When the isolation barrier is Hi-Z).
Table 4-1. LPS Timing Parameters
Parameter LPS = Low propagation delay (with isolation barrier) LPS = High propagation delay (with isolation barrier) Reset active Disable active Setup time when using isolation barrier tLPSL tLPSH tLPS_RESET tLPS_DISABLE tRESTORE Symbol MIN. 0.09 0.09 1.2 25 15 MAX. 1.00 1.00 2.75 30 20 Unit
s s s s s
Figure 4-1. LPS Waveform when Connected to Isolation Barrier
tLPSH
tLPSL
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Data Sheet S16725EJ2V0DS
PD72852A
Figure 4-2. PHY/Link Interface Reset and Disable (a)
D, CTL, LREQ LPS LPS (with isolation barrier) SCLK
Reset
tLPS_RESET
tRESTORE
(b)
D, CTL, LREQ LPS LPS (with isolation barrier) SCLK
Disable
tLPS_DISABLE
tRESTORE
4.2 Link-on Indication
When the power supply of Link is off (LPS is Low and the internal PHY register Link_active bit is 0), the pin LKON outputs a clock of 6.144 MHz according to the following conditions: * Link-on packet is received. * When any bit of the PD72852A PHY register's loop, Pwr_fail, Timeout or Port_event becomes 1, and either LPS or the Link_active bit is 0.
Table 4-2. Link-on Timing
Parameter Frequency Duty Cycle Propagation delay before the Link becomes active (LPS is asserted and the Link_active bit in the PHY register is 1). MIN. 4 40 MAX. 8 60 500 Unit MHz % ns
* If LPS or the Link_active bit is 0, the Link is considered inactive. When the Link is inactive and any of Loop, Pwr_fail, Timeout, Port_event becomes 1, then Link-on is asserted High. * When the Link is active (both LPS and Link_active become 1) and Loop, Pwr_fail, Timeout and Port_event become 1, Status transfer is sent on the PHY/Link interface. * The PD72852A activates the PHY/Link interface when LPS is 1, regardless of the value of the Link active bit.
Data Sheet S16725EJ2V0DS
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PD72852A
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)
The PHY/Link Interface consists of the following operations: * Status transfer to the Link layer controller by CTL * Transmit packet * Receive packet * Request from the Link layer controller by LREQ
4.3.1 CTL0, CTL1
CTL0, CTL1 controls the PHY/Link interface as shown in the Table 4-3.
Table 4-3. CTL Controls PHY
CTL0,CTL1 00 01 10 11 Idle Status Receive Grant Type PHY is in idle function PHY transmitting status information to Link PHY receiving data from the Link PHY allows Link to transmit data Content
This is the operation by which, after Grant, the Link obtains the right to control the interface.
Table 4-4. CTL Controls Link
CTL0,CTL1 00 01 10 11 Idle Hold Transmit Type Content Link completes the packet transmission and releases the PHY/Link interface. 1) Link transmits Hold until the data is ready for transmission. 2) Link transmits the interface connect packet. Link transmits the data to PHY. Not used.
4.3.2 LREQ
Access to the PHY register and the bus is controlled from the Link layer controller through the LREQ pin of PHY.
Figure 4-3. LREQ and CTL Timing
LREQ
LR0
LR1
LR2
LR3
LR(n-2)
LR(n-1)
CTL0,CTL1
CA
CB
CA : CTL before generation of LREQ CB : CTL during LREQ execution
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Data Sheet S16725EJ2V0DS
PD72852A
(1) LREQ format
* Bus Request
Table 4-5. Bus Request Format
Bit 0 1-3 start request Type Signal that starts a request : 1 Bus request type: 000: ImmReq acknowledge packet transmit 001: IsoReq isochronous packet transmit 010: PriReq cycle start packet transmit 011: FairReq asynchronous packet transmit 4-6 speed Transmit speed: 000: 100 Mbps 010: 200 Mbps 100: 400 Mbps other: reserved 7 stop End request signal : 0 (optional) Content
* PHY Register Read Request
Table 4-6. Read Request Register Format
Bit 0 1-3 4-7 8 start request access address stop Type Signal that starts a request : 1 Read Request. 100 : ReadReq PHY register address. End request signal : 0 Content
* PHY Register Write Request
Table 4-7. Write Request Register Format
Bit 0 1-3 4-7 8-15 16 start request access address write data stop Type Signal that starts a request : 1 Write Request. 101 : WriteReq PHY register address. Write data. End request signal : 0 Content
Data Sheet S16725EJ2V0DS
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PD72852A
* Acceleration Controller
Table 4-8. Acceleration Controller Request Format
Bit 0 1-3 4 5 start request access address stop Type Signal that starts a request : 1 110 : Acc Ctrl accelerate controller 0: Accelerate disable 1: Accelerate enable End request signal : 0 Content
Table 4-9. Request Type List
Bit 000 001 010 011 100 101 110 111 ImmReq IsoReq PriReq FairReq RdReg WrReg AccCtrl Type Content Used to acknowledge packet transmit. When Idle is detected, PHY immediately controls the bus. Used to transmit isochronous packet. PHY does arbitration after isochronous gap is detected and acquires the bus. Used for Cycle master request. Fair request. PHY register read request. PHY register write request. Disable/enable of arbitration acceleration. Unused.
For the Link to execute Priority request and Fair, start the request using LREQ when CTL0, CTL1 becomes idle, after one clock. When request is acknowledged, the PD72852A outputs Grant to CTL0, CTL1. The Link of cycle master uses PriReq to transmit the cycle start packet. IsoReq transmits the isochronous packet. IsoReq becomes effective only as follows: * The transmission of the cycle start packet is performed on the same isochronous period as Receive. (The period until the subaction gap is detected.) * During isochronous packet Transmit or Receive. The PD72852A cancels IsoReq with the subaction gap detection or bus reset. To meet the timing, do not issue the IsoReq to PHY when CRC operation is performed. The Link cancel method is described later. After the packet is received, Link issues ImmReq as the acknowledge packet transmission. The purpose is to prevent another node from detecting subaction gap as ACK_RESPONSE_TIME. The PD72852A acquires the bus after packet receive and returns Grant to CTL0, CTL1. When CRC fails, before Link detects Grant, assert 3 Idle cycles to CTL0, CTL1. When the bus reset is generated, the unprocessed requests are canceled. The PD72852A updates the data of the Write request register and the contents of the Read register are changed. The contents of the register of the specified address are output to the Link as a status transfer in the Read request register, When the status transmission is interrupted by transmitting/receiving packets, the status transmission will re-start from the first bit after completing the transmit/receive of the packets. The bus request (ImmReq, IsoReq, PriReg, FairReq) is completed (in case of ImmReq, IsoReq, when the subaction gap is detected) when the packet is transmitted or canceled by canceling the bus request.
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Data Sheet S16725EJ2V0DS
PD72852A
(2) LREQ rules
The Link request and the status of the serial bus are asynchronous; the bus request can be canceled by the status of the serial bus. The following rules apply to a request by LREQ: * Link cannot issue a bus request (ImmReq, IsoReq, PriReq, FairReq) if Grant is given to an LREQ request or until the Link's request is canceled. The request can be canceled by the PD72852A if it detects subaction gap at ImmReq, IsoReq. * Do not issue a RdReg or WrReg request when the status transmission is not completed by the Read request register. * All of the bus requests (ImmReq, IsoReq, PriReq, FairReq) are canceled by a bus reset. In addition, there is a limitation in the request of LREQ according to the state of CTL as shown in Table 4-10.
Table 4-10. Rules for Other Requests
Request State of CTL in CA to which LREQ is allowed when PHY drives CTL Fair, Priority Immediate Idle, Status Receive, Idle wrong wrong LREQ issues permission when Link drives CTL Fair, Priority request cannot be issued until the unprocessed bus request is completed. Link issues the request after completing the decoding of Destination_ID, when the acknowledge packet is ready. After the packet is received, it is necessary to transmit the first bit of the request within four cycles. Isochronous any correct If the isochronous packet transmission is prepared for the isochronous period, it is issued. Do not issue the request to transmit the isochronous packet appending to the currently transmitted isochronous packet (Using Hold). Register Read Register Write AccCtrl any correct any correct Do not issue this request if the unprocessed Read request has not been completed. To set acceleration bit 0: When the isochronous period starts, if the Enab_accel bit is one, Cycle slave should adjust accelerate bit to 0. To set acceleration bit 1: Do not set the cycle master. It is issued when the isochronous period ends. Note
Data Sheet S16725EJ2V0DS
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PD72852A
Table 4-11. PHY Operation Before LREQ Request to the CTL Function Changes
Request State of CTL in CB after LREQ was issued Fair, Priority Receive
* Hold the request if the acceleration of arbitration packet transmitted with
Operation of the PHY
enable is 8 bits (ACK). Except for 8 bits, the requests are ignored.
* Ignore the request when the acceleration of arbitration is disabled.
Grant Idle, Status Immediate Grant Receive Idle, Status Isochronous Transmit Idle (driven by Link) Grant Receive Status Idle Register Read Any (driven by Link) Grant Receive Status Idle Register Write, Acceleration control Any
Arbitration Won. Excluding when the bus reset is generated, Hold the requests.
The packet is being transmitted to Link. Request Hold. Excluding when the bus reset is generated, hold the request. Request Hold. Arbitration Won. Request Hold. Request is ignored when sub-action gap is detected.
Request Hold. Request Hold. Hold the request until the corresponding register value is returned.
Request is completed.
4.3.3 SCLK Timing
Table 4-12. SCLK Timing
Timing Constant BUS_TO_LINK_DELAY DATA_PREFIX_TO_GRANT LINK_TO_BUS_DELAY Comment Period from receiving RX_DATA_PREFIX until Receive to CTL is output. Period when the Grant is output to CTL after TX_DATA_PREFIX is output to a port. Period when TX_DATA_END is output to all ports after transmitting the packet by Link after idle was asserted to CTL. MAX_HOLD Maximum period when Hold can be asserted by Link to confirm Grant. 47 SCLK cycle 2 5 SCLK cycle 25 SCLK cycle MIN. 2 MAX. 9 Unit SCLK cycle
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Data Sheet S16725EJ2V0DS
PD72852A
4.4 Acceleration Control
Enable of ack-acceleration and fly-by on the same isochronous period may create a problem. The isochronous cycle may extend unintentionally when transmitting the asynchronous packet by a node using ack-acceleration and flyby. To avoid this problem, Link should control Disable/Enable of these enhancements (ack-Acceleration, fly-by), by Acceleration Control requests. Cycle master cannot issue the Acceleration Control request. The enhancements should not be used from the generation of the local cycle synchronization event to the confirmation of cycle start. In this period, all Links except for Cycle Master use Acceleration Control as follows: * Do not issue Fair nor Priority request to Link after generating local cycle synchronization, if the Acceleration Control request's Accelerate bit is not set to 0. * Link must not use Hold when transmitting continuous primary asynchronous packet after the Acknowledge packet, except after ack_pending to complete the split transaction. * Ending the Link during the isochronous period issues the acceleration control request to set the Accelerate bit to 1, enabling these enhancements. The PD72852A does not require setting the Acceleration Control during isochronous transmit to enable the isochronous request fly-by acceleration. It is not necessary to issue Acceleration Control request when the cycle master is absent from the serial bus. These enhancements are enabled if the Enab_accel bit in the PHY register is set. The PD72852A supports Variable Acceleration controlled by the Acceleration Control during power-on reset.
Data Sheet S16725EJ2V0DS
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PD72852A
4.5 Transmit Status
Pin D0, D1 of the PD72852A transmits status information to the Link. Status is asserted to CTL while transmitting Status. The status transmission is interrupted if the serial bus receives a packet which contains states other than status to CTL. Between two status transmissions, assert Idle to CTL for at least one SCLK cycle. The PD72852A transmits status in 16 bits as follows: * In response to the register request * After deciding the new Physical_ID for the Self_ID period resetting the bus (after a Self_ID packet is transmitted) The event indication is the only 4-bit transmission of the PD72852A.
Figure 4-4. Status Timing
PHY CTL0,CTL1 PHY D0-D7 00 00 01 01 01
S14, S15
00 00
00 00
S0,S1
S2,S3
Table 4-13. Status Data Format
Bit(s) 0 1 2 3 Name ARB_RESET_GAP SUBACTION_GAP BUS_RESET_START Phy_interrupt Arbitration Reset gap detect Subaction gap detect Bus reset detect Either of the following states is detected:
* The topology of the bus is a loop * Voltage drop on the power cable * Arbitration state machine timeout * Port Event
Description
4-7 8-15
Address Data
PHY register address Register data
The bits already transmitted are set to 0.
Example If the status transmission is interrupted after S0, S1 bit was transmitted, then in the next status transfer,
S0, S1 becomes 0. Therefore one of the following situations will occur when the PD72852A re-transmits status after an interruption of the status transmission: * At least one bit of S0-S3 is 1 * The PHY register data contains the interrupt status information The status transmission always begins with S0, S1. If the Link executes read request, and Subaction gap and arbitration reset gap are detected, priority is given to the transmission of gap status, postponing the response to the register read request.
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Data Sheet S16725EJ2V0DS
PD72852A
4.6 Transmit
The PD72852A arbitrates the serial bus using Link's LREQ. * When the PD72852A acquires the bus, a Grant period of 1 SCLK is executed to CTL0, CTL1. After that, an Idle period of 1 SCLK cycle is executed. * Link controls the interface executing Idle, Hold of Transmit to CTL0, CTL1 after 1 SCLK cycle when Grant from PHY is detected. * Before asserting Hold and Transmit, assert 1 Idle cycle. Do not execute Idle for 2 or more cycles. * If the packet transmit is not ready, the Hold period can be extended up to MAX_HOLD. * The PD72852A outputs DATA_PREFIX to the serial bus while Hold is being asserted to CTL. * When the packet transmit is ready, Link outputs the first bit of the packet and Transmit is asserted to CTL at the same time. * After transmitting the last bit of the packet, Link outputs for Idle or Hold to CTL for 1 cycle. After that, it outputs Idle for 1 cycle. When PHY/Link releases the bus, output Low to CTL and D0-D7 within 1 cycle.
Figure 4-5. Transmit Timing
(a) Single Packet
PHY CTL0,CTL1 PHY D0-D7 Link CTL0,CTL1 Link D0-D7
00 00 ZZ ZZ
11 00 ZZ ZZ
00 00 ZZ ZZ
ZZ ZZ 00 00
ZZ ZZ 01 00
ZZ ZZ 01 00
ZZ ZZ 10 D0
ZZ ZZ 10 D1
ZZ ZZ 10 D2
ZZ ZZ 10 Dn
ZZ ZZ 00 00
ZZ ZZ 00 00
00 00 ZZ ZZ
(b) Concatenated Packet
PHY CTL0,CTL1 PHY D0-D7 Link CTL0,CTL1 Link D0-D7 ZZ ZZ 10 Dn-1 ZZ ZZ 10 Dn ZZ ZZ 01 SP ZZ ZZ 00 00 00 00 ZZ ZZ 00 00 ZZ ZZ 11 00 ZZ ZZ 00 00 ZZ ZZ ZZ ZZ 00 00 ZZ ZZ 01 00 ZZ ZZ 10 D0 ZZ ZZ 10 D1
ZZ ZZ 01 00
Note In case of packet transmission after Grant, before actual transmission, Hold does not need to be asserted.
Link can transmit continuous packets without releasing the bus. * Hold is asserted to CTL. This function is used when the Link transmits continuous packets after acknowledge and isochronous packets. Link outputs the transfer rate signal of the following packet to D0-D7 and asserts Hold simultaneously. * After Hold is detected by MIN_PACKET_SEPARATION, the PD72852A outputs Grant to CTL.
Data Sheet S16725EJ2V0DS
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PD72852A
* Link controls the interface by generating Idle, Hold or Transmit to CTL0, CTL1, after 1 SCLK cycle when Grant from PHY is detected. * Assert 1 Idle cycle before asserting Hold and Transmit (do not output 2 or more Idle cycles). When the packet transmission is not ready, assert Hold. The Hold output period after Grant is detected should not exceed the period provided by MAX_HOLD. The following limitations exist though Link can transmit the concatenated packet with a different transfer rate. Link cannot transmit other than S100 connecting packets after S100 (concatenated) packets have been transmitted. A new request to transmit must be issued in order to transmit S100 packets at a transfer rate of S200 or more. If the Enab_Multi bit in the PHY register is 0, the PD72852A assumes the same speed as the first packet, for all of the concatenated packets. At the end of packet transmission, Link asserts Idle to CTL for a period of 2 cycles. After sampling Idle from Link, the PD72852A asserts Idle to CTL for a period of 1 cycle.
4.7 Cancel
This section describes how Link operates, when after the bus has been acquired by the request of LREQ, there is no data transmission. In this case, a Null packet with no data is transmitted to the serial bus (DATA_PREFIX DATA_END). Following are two method for canceling the Link: 1. As explained in Section 4.6, the Link outputs Idle or Hold, then outputs Transmit to CTL after confirming Grant. Here, the Link asserts Idle for two cycles to CTL, then switches to high impedance. The PD72852A confirms Cancel at the second Idle cycle. To prevent the bus from switching to high impedance, a third Idle cycle is needed.
Figure 4-6. Link Cancel Timing (After Grant)
PHY CTL0,CTL1 PHY D0-D7 00 00 ZZ ZZ 11 00 ZZ ZZ 00 00 ZZ ZZ ZZ ZZ 00 00 ZZ ZZ 00 00 ZZ ZZ 00 00 00 00 ZZ ZZ
Link CTL0,CTL1 Link D0-D7
2. To cancel after asserting Hold, assert Idle between two cycles; it switches to high impedance. This method cancels the packet transmission connection (concatenated) after Grant is received. The PD72852A cancels with the next Idle cycle of Hold. To prevent CTL from switching to high impedance, assert a second Idle cycle.
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Data Sheet S16725EJ2V0DS
PD72852A
Figure 4-7. Link Cancel Timing (After Hold)
PHY CTL0,CTL1 PHY D0-D7 00 00 ZZ ZZ 11 00 ZZ ZZ 00 00 ZZ ZZ ZZ ZZ 00 00 ZZ ZZ 01 00 ZZ ZZ 01 00 ZZ ZZ 00 00 ZZ ZZ 00 00 00 00 ZZ ZZ
Link CTL0,CTL1 Link D0-D7
4.8 Receive
This section shows the operation when the packet is received from the serial bus. * When the PD72852A detects DATA_PREFIX on the serial bus, it asserts receive to CTL and all of the D pins assume the logic value of 1. * The PD72852A shows the speed code of the transfer rate ahead of the packet using bits D0-D7. Transmitting the speed code with the speed signal is the protocol of the PHY/Link interface. The speed code is not included in the CRC calculation. * The PD72852A continues to assert Receive to CTL until the packet is finally transmitted. * Idle is asserted to CTL, indicating completion of the packet transmission.
Figure 4-8. Receive Timing
PHY CTL0,CTL1 (Binary) PHY D0-D7 (Hex) 00 00 10 FF 10 FF 10 SP 10 D0 10 D1 10 Dn 00 00 00 00
The packet transfer rate of the serial bus depends on the topology of the bus. The PD72852A checks if the node can receive at the faster transfer rate. At this time, DATA_PREFIX DATA_END is transmitted to the PD72852A. After DATA_PREFIX is transmitted to the Link, Receive from the serial bus is completed, asserting Idle. Table 4-14 shows the speed code encoding.
Table 4-14. Speed Encoding
D0-D7 Transmitted 00000000 01000000 01010000 11111111 Observed 00xxxxxx 0100xxxx 01010000 11xxxxxx S100 S200 S400 Data Prefix Data rate
Data Sheet S16725EJ2V0DS
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PD72852A
5. CABLE PHY PACKET
The node on the serial bus transmits and receives the PHY packet to control the bus. The PHY packet is composed of 2 quadlets (64-bit); the second quadlet (32-bit) contains the inverse value of the first quadlet. The PHY packet is transmitted at a transfer rate of S100. All of the PHY packets received from the serial bus are transmitted to the Link. Though the PHY packet from the PD72852A is transmitted to the Link, the PHY packet which was transmitted from the Link of the node is not transmitted to the Link. There are four types of PHY packets, as follows: * Self_ID packet * Link-on packet * PHY configuration packet * Extended PHY packet The Self_ID packet transmitted automatically by the PD72852A is also transmitted to the Link of a local node. The PD72852A PHY packet Receive from the serial bus operates similar to the PHY packet transmitted by the Link (when the packet transmission to the Link is executed).
5.1 Self_ID Packet
During the Self_ID phase of the initialization or when the Ping packet responds, the PD72852A transmits the Self_ID packet.
Figure 5-1. Self_ID Packet Format
10 phy_ID 0 L gap_cnt sp rsv c pwr p0 p1 p2 i
m
Logical Inverse of the first quadlet
Table 5-1. Self_ID Packet
Field phy_ID L gap_cnt sp c pwr Physical ID of the node. Logical product of Link_active and LPS in the PHY register. Gap_count value in the PHY register. Physpeed 10 (corresponds to 98.304, 196.608, 393.216 Mbps). C bit values in the PHY register. pwr value in the PHY register. 000: The node does not need the power supply. No power repeat. 001: Obtains power supply for the node. Can supply 15 W or more. 010: Obtains power supply for the node. Can supply 30 W or more. 011: Obtains power supply for the node. Can supply 45 W or more. 100: The node consumes 3 W maximum power. 110: The node consumes 3 W maximum power. At least 3 W are necessary to enable Link. 111: The node consumes 3 W maximum power. At least 7 W are necessary to enable Link. i m rsv It shows that the node issued Bus Reset and the bus was reset. Read as 0. Read as 00. Description
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Data Sheet S16725EJ2V0DS
PD72852A
5.2 Link-on Packet
The PD72852A outputs the Link-on signal of 6.144 MHz from the pin LKON when receiving the Link-on packet.
Figure 5-2. Link-on Packet Format
01 phy_ID 0000 0000 0000 0000 0000 0000
Logical Inverse of the first quadlet
Table 5-2. Link-on Packet
Field phy_ID Description Physical_ID of the destination of the Link-on packet
5.3 PHY Configuration Packet
Use the PHY configuration packet to set the gap count for the bus.
Figure 5-3. PHY Configuration Packet Format
00 root_ID R T gap_cnt 0000 0000 0000 0000
Logical Inverse of the first quadlet
Table 5-3. PHY Configuration Packet
Field root_ID R T Description Sets the Physical_ID node as root contender (for the next reset). When this bit is set to 1 and the Phyisical_ID of the node corresponds to the rootID of this packet, the
PD72852A sets the force_root bit. The force_root bit is cleared if there is discrepancy.
If this bit is 1, the gap_cnt value of this packet is used as the gap_count value. The gap_count value must not be cleared by the following bus reset, set the gap_count_reset_disable flag in the PD72852A to TRUE. gap_cnt When this packet is received, the gap count is set to this value. While it remains effective for the next bus reset, it will be cleared by the second bus reset to 3FH.
Remark Applying 0 to both R,T, regards the following packets as extended PHY packets, the PHY configuration is not
recognized.
5.4 Extended PHY Packet
An extended PHY packet is defined when both the R (in the PHY configuration packet) and T bits are transmitted as 0. The extended PHY packet does not influence the force_root_bit and the gap_count bit on any node. Following are the types of extended PHY packets: * Ping packet * Remote access packet * Remote reply packet * Remote command packet * Remote confirmation packet * Resume packet
Data Sheet S16725EJ2V0DS
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PD72852A
5.4.1 Ping Packet
When the PD72852A receives the Ping packet, it will transmit the Self_ID packet within the RESPONSE_TIME.
Figure 5-4. Ping Packet Format
00 phy_ID 00 type (0) 00 0000 0000 0000 0000
Logical Inverse of the first quadlet
Table 5-4. Ping Packet
Field phy_ID type Description Physical ID of the destination node of the Ping packet Indicates that there is a Ping packet with a value of 0
5.4.2 Remote Access Packet
The Remote access packet reads information in the PHY register of another node. The PHY specified by the Remote access packet transmits the value in the register using the Remote Reply packet.
Figure 5-5. Remote Access Packet Format
00 phy_ID 00 type page port reg reserved
Logical Inverse of the first quadlet
Table 5-5. Remote Access Packet
Field phy_ID type page port reg Description Physical ID of the destination node of the Remote access packet 1 = read register (base register), 5 = read register (page register) Specifies the page of the PHY register Specifies the register of each port in the PHY register Specifies the address when reading the base register. In case of the Page and port registers, specifies the address with 1000+reg.
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Data Sheet S16725EJ2V0DS
PD72852A
5.4.3 Remote Reply Packet
The PD72852A transmits the value in the register by using the Remote reply packet as a response to the Remote access packet.
Figure 5-6. Remote Reply Packet Format
00 phy_ID 00 type page port reg data
Logical Inverse of the first quadlet
Table 5-6. Remote Reply Packet
Field phy_ID type page port reg data Description Physical ID of the node (Node's original packet transmit) 3 = register read (base register), 7 = read register (page register) Used when specifying the page of the PHY register Used to specify the register of each port in the PHY register Specifies the address when reading the base register. In case of the Page and port registers, specify the address with 1000+reg. Contents of the specified register
5.4.4 Remote Command Packet
Use the Remote command packet to operate the function of the port of the PHY of another node.
Figure 5-7. Remote Command Packet Format
00 phy_ID 00 type(8) 000 port 0000 0000 cmnd
Logical Inverse of the first quadlet
Table 5-7. Remote Command Packet
Field phy_ID type port cmnd Physical ID of the destination packet Extended PHY packet type; set to 8 for Remote command packet Port of the PHY of the operating node Command 0: NOP 1: Disables the port after transmission of the TX_DISABLE_NOTIFY 2: Suspend initiator 4: Clears to 0 the Fault bit of the port 5: Enables the port 6: Resumes the port Description
Data Sheet S16725EJ2V0DS
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PD72852A
5.4.5 Remote Confirmation Packet
The PD72852A transmits the Remote confirmation when the Remote command packet is received, responding whether cmnd can be executed.
Figure 5-8. Remote Confirmation Packet Format
00 phy_ID 00 type(A16) 000 port 000 f c b d ok cmnd
Logical Inverse of the first quadlet
Table 5-8. Remote Confirmation Packet
Field phy_ID type port f c b d ok cmnd Description Physical ID of the node (node's original packet transmit) Extended PHY packet type; set to A16 for Remote confirmation packet Port set from the Remote command packet Fault bit value of the PHY register of this port Connected bit value of the PHY register of this port Bias bit value of the PHY register of this port Disable bit value of the PHY register of this port 1 indicates executing; otherwise it is 0 Specifies the command value with the Remote command packet
5.4.6 Resume Packet
When the PD72852A receives the Resume packet, all of the ports that were suspended resume the connection. The Resume packet does the broadcast.
Figure 5-9. Resume Packet Format
00 phy_ID 00 type (F16) 00 0000 0000 0000 0000
Logical Inverse of the first quadlet
Table 5-9. Resume Packet
Field phy_ID type Physical ID of the original packet transmit Extended PHY packet type; set to F16 for Resume packet Description
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Data Sheet S16725EJ2V0DS
PD72852A
6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VDDm VIN VOUT Tstg Condition Rating -0.5 to +4.6 -0.5 to VDD+0.5 -0.5 to VDD+0.5 -40 to +125 Unit V V V
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. A CMOS device may cause unusual operation or destruction by Latch-up phenomenon. For your safety, be careful of the factor (serge, noise, static electricity) considered as external stress to Input/Output pins. In order to avoid outbreak of heat/destruction of the device/board/equipment by an over-current continuing input, please prepare the current restrictions below 1.5 [A] as VCC input.
Recommended Operating Ranges
Parameter Power supply voltage Symbol VDD Condition Source power node Non-source power node Operating temperature Power dissipation TA PD MIN. 3.0 2.7
Note
TYP. 3.3 3.0
MAX. 3.6 3.6 70.0 440
Unit V V
C
0.0
mW
Note For a node does not source power.
Data Sheet S16725EJ2V0DS
39
PD72852A
DC Characteristics
Common
Parameter Supply current Symbol IDD
Note 1 Note 2 Note 3 Note 4 Note 5
Condition
MIN.
TYP. 68 60 41 31 115
MAX.
Unit mA mA mA mA
A
Notes 1. Transmit maximum packet (all ports transmitting maximum size isochronous packet - 4096 bytes, sent on
every isochronous interval, S400, data value of CCCCCCCCH), VDD = 3.3 V, TA = 25C
2. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and
transmitting on the other port), VDD = 3.3 V, TA = 25C
3. Idle (one port receiving and one port transmitting cycle starts), VDD = 3.3 V, TA = 25C 4. 1 port receiving cycle start packet only, VDD = 3.3 V, TA = 25C 5. Suspend mode, VDD = 3.3 V, TA = 25C PHY/Link Interface
Parameter High-level output voltage Symbol VOH Condition CTL0, CTL1, D0-D7, LKON, SCLK, IOH = -9 mA, VDD > 3 V CTL0, CTL1, D0-D7, LKON, SCLK, IOH = -4 mA, VDD = 2.7 V Low-level output voltage VOL CTL0, CTL1, D0-D7, LKON, SCLK, IOH = +9 mA, VDD > 3 V CTL0, CTL1, D0-D7, LKON, SCLK, IOH = +4 mA, VDD = 2.7 V High-level input voltage Low-level input voltage High-level input voltage (schmitt) Low-level input voltage (schmitt) High-level input current VIH VIL VIHS VILS IIH
LPS, SPD, DIRECT, PC0-PC2, SUS/RES, CMC LPS, SPD, DIRECT, PC0-PC2, SUS/RES, CMC
MIN. VDD-0.45 VDD-0.4
TYP.
MAX.
Unit V V
0.4 0.4 0.7VDD 0.2VDD 0.456VDD +0.3 0.456VDD -0.9 -10 -10 0.456VDD +0.9 0.456VDD -0.3
V V V V V V
CTL0, CTL1, D0-D7, LREQ, VDD > 3 V CTL0, CTL1, D0-D7, LREQ, VDD > 3 V CTL0, CTL1, D0-D7, VI = VDD, DIRECT = 0 V
LPS, SPD, DIRECT, PC0-PC2, SUS/RES, CMC, VI = VDD
A A
Low-level input current
IIL
CTL0, CTL1, D0-D7, LKON, SCLK, VI = 0 V, DIRECT = 0 V
LPS, SPD, DIRECT, PC0-PC2, SUS/RES, CMC, VI = 0 V
10 10
A A
40
Data Sheet S16725EJ2V0DS
PD72852A
Cable Interface
Parameter Differential input voltage Symbol VID Condition Cable input, 100 Mbps operation Cable input, 200 Mbps operation Cable input, 400 Mbps operation TpB common mode input voltage VICM 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Differential output voltage TpA common mode output voltage VOD VOCM Cable output (Test load 55 ) 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling TpA common mode output current ICM 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Power status threshold voltage TpBias output voltage VTH VTPBIAS CPS 1.665 MIN. 142 132 118 1.165 0.935 0.523 172.0 1.665 1.438 1.030 -0.81 -4.84 -12.40 TYP. MAX. 260 260 260 2.515 2.515 2.515 265.0 2.015 2.015 2.015 +0.44 -2.53 -8.10 7.5 2.015 Unit mV mV mV V V V mV V V V mA mA mA V V
Data Sheet S16725EJ2V0DS
41
PD72852A
AC Characteristics
PHY/Link Interface
Parameter D, CTL, LREQ setup time D, CTL, LREQ hold time D, CTL output timing SCLK cycle time SCLK high level time SCLK low level time LKON cycle time Symbol tSU tHD tD tSCLK tSCLKH tSCLKL tLINKON Condition MIN. 5 0 0.5 20 9 9 160 11 11 9 TYP. MAX. Unit ns ns ns ns ns ns ns
Link Interface Timing (SCLK, LKON)
SCLK tSCLKH tSCLK tSCLKL
LKON tLINKON
42
Data Sheet S16725EJ2V0DS
PD72852A
Link Interface Timing (CTL, D)
SCLK
tD
Transmit
tD
tD
CTL0,CTL1
tD D0-D7
tD
tD
tSU
Receive
tH
CTL0,CTL1 tSU tH
D0-D7
Link Interface Timing (LREQ)
SCLK tSU tH
LREQ
Cable Interface
Parameter TpA, TpB transfer jitter TpA strobe, TpB data transfer TPA, TPB rise time/fall time Symbol tJITTER tSKEW tR/tF Condition Between TpA and TpB Between TpA and TpB 10 % to 90 %, via 55 and 10 pF S100 S200 S400 0.5 0.5 0.5 Speed MIN. TYP. MAX. 0.15 0.10 3.2 2.2 1.2 Unit ns ns ns ns ns
Data Sheet S16725EJ2V0DS
43
PD72852A
7. APPLICATION CIRCUIT EXAMPLE
* IEEE1394 Interface
0.1 F
5.1 k 270 pF
5.1 k 270 pF
1 F
1 F
TpBias1 AVDD TpA1p TpA1n TpB1p TpB1n AGND TpBias0 AVDD TpA0p TpA0n TpB0p TpB0n AGND RI1 AGND
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
56 56
56 56
56 56
56 56
9.1 k (0.5%)
0.1 F
Note
Note
100 k
22 F
DGND SCLK IC(DL) DVDD CTL0 CTL1 DGND D0 D1 DVDD D2 D3 DGND D4 D5 DGND
0.1 F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DVDDPOWER (3.3 V)
0.1 F
0.1 F
0.1 F
GND
0.1 F
49 50 51 52 53 0.1 F 54 0.1 F 55 0.1 F 56 57 58 59 60 61 0.1 F 62 63 64
AGND DIRECT IC(AL) AGND AGND AVDD RESETB DVDD DGND LKON LPS DVDD SPD FNSel LREQ DGND
CPS AVDD CMC IC(AL) PC2 PC1 PC0 AVDD AGND XI XO DGND DVDD SUS/RES D7 D6
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
390 k
(Cable Supply Voltage)
VP
Power Class Programming 0.1 F 24.576 MHz 10 pF 10 pF 0.1 F
22 F AVDDPOWER (3.3 V) GND
Note
Common mode choke. Recommendation : TDK Part No. ACM2012-121 : MURATA Part No.PLP31DN161SL4
44
Data Sheet S16725EJ2V0DS
PD72852A
8. PACKAGE DRAWING
64-PIN PLASTIC LQFP (10x10)
A B
48 49
33 32 S P
detail of lead end
C
D
T
R 64 1 F G H I
M
L U
17 16
Q
J
K S
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.4 0.10.05 3 +4 -3 1.50.10 0.25 0.60.15 S64GB-50-8EU-2
N
NOTE
S
M
Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
Data Sheet S16725EJ2V0DS
45
PD72852A
9. RECOMMENDED SOLDERING CONDITIONS
The PD72852A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 9-1. Surface Mounting Type Soldering Conditions
PD72852AGB-8EU: 64-pin plastic LQFP (10 x 10)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher). Count: three times or less Exposure limit: 3 daysNote (after that prebake at 125C for 10 hours) Partial heating Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) -- Soldering Conditions Recommended Condition Symbol IR35-103-3
Note After opening the dry pack, store it at 25C or less and 65 % RH or less for the allowable storage period.
46
Data Sheet S16725EJ2V0DS
PD72852A
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 PAY ATTENTION TO CHARGING WITH STATIC ELECTRICITY OF THE DEVICE OR THE SURFACE OF THE DEVICE PACKAGE In case the handing of this product and the production manufacturing process, please use the ionizer for this device to eliminate static electricity.
Data Sheet S16725EJ2V0DS
47
PD72852A
FireWire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation. Intel is a trademark of Intel Corporation.
* The information in this document is current as of March, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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